THS1206EP

12BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOGTODIGITAL CONVERTERS

SGLS126A − JULY 2002 − REVISED FEBRUARY 2003

21

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DATA_AV type

Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of

control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register

determines the polarity of DATA_AV. This is shown in Table 14.

Table 14. DATA_AV Type

BIT 5

DATA_P

BIT 4

DATA_T

DATA_AV TYPE

0

0

Active low level

0

1

Active low pulse

1

0

Active high level

1

1

Active high pulse

The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive independent

of the DATA_T selection (pulse or level).

If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling

edge of READ). The trigger condition is checked again after TL reads.

If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in

continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode.

The next DATA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the TL values,

written into the FIFO before, were read out by the processor.