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STM32F427NET6TR 数据表(PDF) 69 Page - STMicroelectronics |
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STM32F427NET6TR 数据表(HTML) 69 Page - STMicroelectronics |
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69 / 231 page  DocID024030 Rev 6 69/231 STM32F427xx STM32F429xx Pinouts and pin description 83 4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is delivered in an WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low). 7. PI0 and PI1 cannot be used for I2S2 full-duplex mode. 8. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. |
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