STM32F427NET6 datasheet(154/231 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F427xx STM32F429xx

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Equation 1: RAIN max formula

tlat(2)

Injection trigger conversion

latency

fADC = 30 MHz

0.100

µs

3(5)

1/fADC

tlatr(2)

Regular trigger conversion

latency

fADC = 30 MHz

0.067

µs

2(5)

1/fADC

tS(2)

Sampling time

fADC = 30 MHz

0.100

µs

480

1/fADC

tSTAB(2) Power-up time

µs

tCONV(2)

Total conversion time (including

sampling time)

fADC = 30 MHz

12-bit resolution

0.50

16.40

µs

fADC = 30 MHz

10-bit resolution

0.43

16.34

µs

fADC = 30 MHz

8-bit resolution

0.37

16.27

µs

fADC = 30 MHz

6-bit resolution

0.30

16.20

µs

9 to 492 (tS for sampling +n-bit resolution for successive

approximation)

1/fADC

fS(2)

Sampling rate

(fADC = 30 MHz, and

tS = 3 ADC cycles)

12-bit resolution

Single ADC

Msps

12-bit resolution

Interleave Dual ADC

mode

3.75

Msps

12-bit resolution

Interleave Triple ADC

mode

Msps

IVREF+(2)

ADC VREF DC current

consumption in conversion

mode

-300

500

µA

IVDDA(2)

ADC VDDA DC current

consumption in conversion

mode

-1.6

1.8

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:

Internal reset OFF).

2. Guaranteed by characterization results.

3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.

5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 74.

Table 74. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RAIN

k0,5

–

()

fADC CADC

()

-------------------------------------------------------------- R

ADC

–

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