STM32F427NET6 datasheet(39/231 Pages) STMICROELECTRONICS

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STM32F427xx STM32F429xx

Functional overview

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

3.33

Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator. The major features are:

•

Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

4 bidirectional endpoints

•

8 host channels with periodic OUT support

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

3.34

Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.

The USB OTG HS supports both full-speed and high-speed operations. It integrates the

transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)

for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an

external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

1.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock

that is generated by a PLL connected to the HSE oscillator.

The major features are:

•

Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

6 bidirectional endpoints

•

12 host channels with periodic OUT support

•

Internal FS OTG PHY support

•

External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

•

HNP/SNP/IP inside (no need for any external resistor)

•

for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

STM32F427NET6 数据表(PDF) 39 Page - STMicroelectronics

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