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STM32F427NET7 数据表(PDF) 174 Page - STMicroelectronics |
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STM32F427NET7 数据表(HTML) 174 Page - STMicroelectronics |
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174 / 231 page  Electrical characteristics STM32F427xx STM32F429xx 174/231 DocID024030 Rev 6 Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings Table 96. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2THCLK − 1 - ns t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0.5 ns td(CLKH- NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -ns td(CLKL- NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL- NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) THCLK − 0.5 - ns td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+2 ns td(CLKH- NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 - ns tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 5 - ns |
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