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STM32F427NET7 数据表(PDF) 173 Page - STMicroelectronics

部件名 STM32F427NET7
功能描述  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
PDF  231 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F427NET7 数据表(HTML) 173 Page - STMicroelectronics

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STM32F427xx STM32F429xx
Electrical characteristics
192
Table 95. Synchronous multiplexed PSRAM write timings(1)(2)
1. CL = 30 pF.
2. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK − 1
-
ns
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
-
1.5
ns
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
THCLK
-ns
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
0
ns
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
0
-
ns
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
0
ns
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
THCLK
-ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
-
0
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high
THCLK−0.5
-
ns
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
ns
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid
0
-
ns
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low
-
3
ns
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
0
-
ns
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
THCLK−0.5
-
ns
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
4
-
ns
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
0
-
ns



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