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STM32F427NET7 数据表(PDF) 169 Page - STMicroelectronics |
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STM32F427NET7 数据表(HTML) 169 Page - STMicroelectronics |
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169 / 231 page  DocID024030 Rev 6 169/231 STM32F427xx STM32F429xx Electrical characteristics 192 Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms Table 92. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 4THCLK 4THCLK+0.5 ns tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK − 1THCLK+0.5 ns tw(NWE) FMC_NWE low time 2THCLK 2THCLK+0.5 ns th(NE_NWE) FMC_NWE high to FMC_NE high hold time THCLK -ns tv(A_NE) FMC_NEx low to FMC_A valid - 0 ns tv(NADV_NE) FMC_NEx low to FMC_NADV low 0.5 1 ns tw(NADV) FMC_NADV low time THCLK − 0.5 THCLK+ 0.5 ns th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) THCLK − 2-ns th(A_NWE) Address hold time after FMC_NWE high THCLK -ns th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK − 2-ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns tv(Data_NADV) FMC_NADV high to Data valid - THCLK +1.5 ns th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 - ns |
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