STM32F427NET7 datasheet(227/231 Pages) STMICROELECTRONICS

227 / 231 page

DocID024030 Rev 6

227/231

STM32F427xx STM32F429xx

Revision history

230

24-Jan-2014

Added STM32F429xE part numbers featuring 512 Mbytes of Flash

memory and UFBGA169 package.

Added LPSDR SDRAM.

Changed INTN into INTR in Figure 4: STM32F427xx and

STM32F429xx block diagram.

Added note 4 in Table 2: STM32F427xx and STM32F429xx features

and peripheral counts.

Updated Section 3.15: Boot modes.

Updated for PA4 and PA5 in Table 10: STM32F427xx and

STM32F429xx pin and ball definitions.

Added VIN for BOOT0 pins in Table 14: Voltage characteristics.

Updated Note 6., added Note 1.,and updated maximum VIN for B pins

in Table 17: General operating conditions.

Updated maximum Flash memory access frequency with wait states

for VDD =1.8 to 2.1 V in Table 18: Limitations depending on the

operating power supply range.

Updated Table 24: Typical and maximum current consumption in Run

mode, code with data processing running from Flash memory (ART

accelerator enabled except prefetch) or RAM and Table 25: Typical

and maximum current consumption in Run mode, code with data

processing running from Flash memory (ART accelerator disabled).

Updated Table 30: Typical current consumption in Run mode, code

with data processing running from Flash memory or RAM, regulator

ON (ART accelerator enabled except prefetch), VDD=1.7 V, Table 31:

Typical current consumption in Run mode, code with data processing

running from Flash memory, regulator OFF (ART accelerator enabled

except prefetch), and Table 32: Typical current consumption in Sleep

mode, regulator ON, VDD=1.7 V.

Updated Table 57: Output voltage characteristics.

Updated Table 58: I/O AC characteristics. Added Figure 35.

Updated th(SDA), tr(SDA) and tr(SCL) and added tSP in Table 61: I2C

characteristics.

Updated fSCK in Table 62: SPI dynamic characteristics.

Updated Table 70: Dynamic characteristics: USB ULPI.

Updated Section 6.3.26: FMC characteristics conditions. Updated

Figure 73: SDRAM read access waveforms (CL = 1) and Figure 74:

SDRAM write access waveforms. Added Table 103: LPSDR SDRAM

read timings and Table 105: LPSDR SDRAM write timings. Updated

Table 102: SDRAM read timings and Table 104: SDRAM write timings

and added note 2.Table 108: Dynamic characteristics: SD / MMC

characteristics.

Table 124. Document revision history

Date

Revision

Changes

STM32F427NET7 数据表(PDF) 227 Page - STMicroelectronics

STM32F427NET7 数据表(HTML) 227 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载