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November 2004

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LOW POWER DISSIPATION:

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HIGH NOISE IMMUNITY:

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POWER DOWN PROTECTION ON INPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

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IMPROVED LATCH-UP IMMUNITY

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DESCRIPTION

The 74VHC573 is an advanced high-speed

CMOS OCTAL D-TYPE LATCH with 3 STATE

OUTPUTS NON INVERTING fabricated with

sub-micron silicon gate and double-layer metal

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input precisely. When

the LE is taken low, the Q outputs will be latched

precisely at the logic level of D input data. While

the (OE) input is low, the 8 outputs will be in a

normal logic state (high or low logic level) and

while (OE) is in high level, the outputs will be in a

high impedance state.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74VHC573

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTS NON INVERTING

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74VHC573MTR

TSSOP

74VHC573TTR

TSSOP

SOP

Rev. 5