74VHC573

2/14

Figure 2: Input Equivalent Circuit

Table 2: Pin Description

Table 3: Truth Table

X : Don’t Care

Z : High Impedance

* : Q Outputs are Latched at the time when the LE input is taken low logic level.

Figure 3: Logic Diagram

This logic diagram has not be used to estimate propagation delays

PIN N°

SYMBOL

NAME AND FUNCTION

1OE

3 State Output Enable

Input (Active LOW)

2, 3, 4, 5, 6,

7, 8, 9

D0 to D7

Data Inputs

12, 13, 14,

15, 16, 17,

18, 19

Q0 to Q7

3-State Latch Outputs

11

LE

Latch Enable Input

10

GND

Ground (0V)

20

Positive Supply Voltage

INPUTS

OUTPUT

OE

LE

D

Q

HX

X

Z

LL

X

NO CHANGE*

LHL

L

L

HHH