TLV1171

SBVS177 – APRIL 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

PRODUCT

VOUT

TLV1171vvyyyz

VV is the nominal output voltage (for example, 33 = 3.3 V).

YYY is the package designator.

Z is the package quantity. Use R for reel (2500 pieces), and T for tape (250 pieces).

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

At TJ = +25°C, unless otherwise noted. All voltages are with respect to GND.

VALUE

MIN

MAX

UNIT

Input voltage range, VIN

–0.3

+6.0

V

Voltage

Output voltage range, VOUT

–0.3

+6.0

V

Current

Maximum output current, IOUT

Internally limited

Output short-circuit duration

Indefinite

Continuous total power dissipation

PDISS

See Thermal Information Table

Operating junction, TJ

–55

+150

°C

Temperature

Storage, Tstg

–55

+150

°C

Human body model (HBM)

2

kV

QSS 009-105 (JESD22-A114A)

Electrostatic discharge (ESD)

ratings

Charged device model (CDM)

500

V

QSS 009-147 (JESD22-C101B.01)

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

THERMAL INFORMATION

TLV1171

THERMAL METRIC(1)

DCY (SOT223)

UNITS

3 PINS

θJA

Junction-to-ambient thermal resistance

62.9

θJCtop

Junction-to-case (top) thermal resistance

47.2

θJB

Junction-to-board thermal resistance

12.0

°C/W

ψJT

Junction-to-top characterization parameter

6.1

ψJB

Junction-to-board characterization parameter

11.9

θJCbot

Junction-to-case (bottom) thermal resistance

N/A

space

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

2

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