PM6680ATR datasheet(42/48 Pages) STMICROELECTRONICS

42 / 48 page

Design guidelines

PM6680A

42/48

Equation 41

(Let's assume Tmax=75 °C in RDSon calculation). We choose standard value

RCSENSE = 560 Ω.

Input capacitor

Maximum input capacitor RMS current is about 1.084 A. Then ICINRMS > 1.084 A

We put two 10

µF ceramic capacitors with Irms = 1.5 A.

Synchronous rectifier

OUT1: Shottky diode STPS1L40M

OUT2: Shottky diode STPS1L40M

Integrator loop

(Refer to figure 14)

OUT1: The ripple is smaller than 40 mV, then the virtual ESR network is required.

CINT = 1.5 nF; Cfilt = 47 pF; RINT = 1.1 kΩ

OUT2: The ripple is smaller than 40 mV, then the virtual ESR network is required.

CINT =1.5 nF; Cfilt =47 pF; RINT = 820 Ω

Output feedback divider

(Refer to figure 6)

OUT1: R1 = 10 k

Ω; R2 = 27 kΩ

OUT2: R1 = 10 k

Ω; R2 = 10 kΩ

Layout guidelines

The layout is very important in terms of efficiency, stability and noise of the system. It is

possible to refer to the PM6680A demoboard for a complete layout example.

For good PC board layout follows these guidelines:

●

Place on the top side all the power components (inductors, input and output capacitors,

MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve

a layer to PGND plan. The PGND plan is the same for both the switching sections.

●

AC current paths layout is very critical (seeFigure 41). The first priority is to minimize

their length. Trace the LS MOSFET connection to PGND plan as short as possible.

Place the synchronous diode D near the LS MOSFET. Connect the LS MOSFET drain

to the switching node with a short trace.

●

Place input capacitors near HS MOSFET drain. It is recommended to use the same

input voltage plan for both the switching sections, in order to put together all input

capacitors.

●

Place all the sensitive analog signals (feedbacks, voltage reference, current sense

paths) on the bottom side of the board or in an inner layer. Isolate them from the power

top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in

one point (a multiple vias connection is preferable to a 0 ohm resistor connection) near

the PGND device pin. Place the device on the top or on the bottom size and connect

the exposed pad and the SGND pins to the SGND plan (see Figure 41).

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