IP1718 LF
Preliminary Data Sheet
27/33
January 27, 2005
Copyright © 2003, IC Plus Corp.
IP1718 LF-DS-R05
Register
Address
Register Description
Attribute
Default
value
80H
CPU read/write PHY register command
bit[4:0] : the PHY address
bit[9:5] : the MII register address
bit[12:10] : (Reserved)
bit[13] : 1: the read/write command has been completed
0: not yet
bit[14] : 0: read operation,
1: write operation
bit[15] : the read/write command trigger
0: IDLE or command complete
1: Start command
R/W
16’d0
81H
CPU read/ write PHY register data
bit[15:0] : the data to be written into PHY register for write command.
The last data read from PHY register read command.
R/W
16’d0
82H
Port status of port4~pot1, 4 bit per port
bit[3:0] : {flow_ctrl, duplex, speed, link}. Bit[15:4] indicates the
operating mode for port4 to port2.
R
16’d0
83H~85H
Port status for port5 to port16.
R
16’d0
88H
Link status port18~pot17, 4 bit per port
bit[7:0] : {flow_ctrl, duplex, speed, link}
Bit0~bit4 stands fot the operating mode for port 17.
R
16’d0
90H
bit[15] : share memory over-flow indication
bit[14] : share memory under-flow indiaction
bit[10:0] : share memory current page count
R
16’hxx
91H
Reserved for test
Reserved 16’hxx
92H
Reserved for test
Reserved 16’hxx
A0H
bit[0] : Interrupt enable for completing CPU r/w SMI command
1: Enable interrupt indication;
0: No interrupt
bit[4] : Status of the CPU r/w SMI command
1: Command completed;
0: Command processing
R/W
5’h00
A1
Do not access to this register.
Reserved 16’h000f
A2H
bit[0] : Software reset. Writing a “1” to this bit will reset the IP1718
LF. This bit is self-cleared to “0”.
W
1’b0
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