35 / 48 page
IP1001 LF
Data Sheet
35/48
Dec. 18, 2007
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
4.10
1000BASE-T Control Register (Reg9)
Bit
Name
Description
Type
HW
Reset
SW
Reset
9[7:0]
Reserved
Ignore when read
R/W
Reserved to
0x00
9.8
1000BASE-T Half
Duplex
1: Advertise 1000BASE-T half duplex capable
0: Not advertise
R/W
1
0
9.9
1000BASE-T Full
Duplex
1: Advertise 1000BASE-T full duplex capable
0: Not advertise
R/W
1
0
9.10
Port Type
1: Prefer multi-port device (MASTER)
0: Prefer single-port device (SLAVE)
R/W
1
0
9.11
Configuration
Value
1: Manual configure as MASTER
0: Manual configure as SLAVE
It is valid only if bit 9.12 is set to 1.
R/W
0
0
9.12
Manual
Configuration
Enable
1: Manual Configuration Enabled
0: Manual Configuration Disabled
R/W
0
0
1000BASE_T test mode defined in IEEE802.3
clause 40.6.
9[15:13] Mode
000
Normal Mode
001
Test Mode 1
- Transmit waveform test
010
Test Mode 2 - Transmit Jitter test in
MASTER mode
011
Test Mode 3 - Transmit Jitter test in
SLAVE mode
100
Test Mode 4 - Transmit distortion
test
9[15:13] Test mode
Others
Reserved
R/W
000
000
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
