IP1001 LF
Data Sheet
5.3.2
MII Timing
a. Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TTclk1
Period of transmit clock in 100M mode
-
40
-
ns
TTclk1
Period of transmit clock in 10M mode
-
400
-
ns
TXEN, TXD to TX_CLK setup time
(TXPHASE_SEL=0, no clock delay added)
-0.65
ns
Ts1
TXEN, TXD to TX_CLK setup time
(TXPHASE_SEL=1, clock delay added)
3.35
ns
TXEN, TXD to TX_CLK hold time
(TXPHASE_SEL=0, no clock delay added)
0.2
ns
Th1
TXEN, TXD to TX_CLK hold time
(TXPHASE_SEL=1, clock delay added)
4.2
ns
MII_TXC LK
TXE N , TXD [3:0]
T s1
T h1
T Tclk1
b. Receive Timing
Symbol
Description
Min.
Typ.
Max.
Unit
TRclk1
Period of receive clock in 100M mode
-
40
-
ns
TRclk1
Period of receive clock in 10M mode
-
400
-
ns
MII_RXCLK rising edge to RXDV, RXD
(RXPHASE_SEL=0, no clock delay added)
-0.4
0
0.4
ns
Td1
MII_RXCLK rising edge to RXDV, RXD
(RXPHASE_SEL=1, clock delay added)
3.6
4
4.4
ns
Td1
RX_CLK
RXDV, RXD[3:0]
TRclk1
Dec. 18, 2007
44/48
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
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