IP101A LF
Data Sheet
23/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
MDC, Management Data Clock, provides management data clock at maximum of 10MHz as a reference
for MDIO, Management Data Input/Output. CRS, Carrier Sense, is used for signaling data transmission is
in process while COL, Collision, is used for signaling the occurrence of collision during transmission.
Transmitting a packet, MAC will first assert TX_EN and convert the information into 4 bit wide data and
then pass the data to IP101A LF. IP101A LF will sample the data according to TX_CLK until TX_EN is low.
While receiving a packet, IP101A LF asserts RX_DV high when data present in the medium through
RXD[3:0] bus lines. IP101A LF samples received data according to RX_CLK until the medium is back to
idle state.
RMII Interface
Reduced Media Independent Interface (RMII) is defined to provide a fewer pins data transmission
condition. The management interface, MDC and MDIO, are identical to the MII defined in IEEE 802.3.
RMII supports 10/100Mb data rates and the clock source is provided by a single 50MHz clock from either
external or within IP101A LF. This clock is used as reference for transmit, receive and control. RMII
provides independent 2 bit wide transmit and receive data path, i.e., TXD[1:0] and RXD[1:0]. CRS_DV is
asserted when the receive medium is not idle and de-asserted when the medium is idle.
Before any transmission occurs, CRS_DV should be de-asserted and value “00” should be present in
both TXD[1:0] and RXD[1:0]. When transmission begins, IP101A LF will send “01” (TXD[1:0] = 01) for
preamble to indicate SFD, and also assert TX_EN synchronous with first nibble of the preamble. TX_EN
should be de-asserted until the end of the data transmission. At receiving mechanism, by receiving “01”
means a valid data is available. If False carrier is detected, RXD[1:0] shall be “10” until the end of the
transmission.
At 10Mbps mode, every 10
th cycle of REF_CLK will be sampled in RXD[1:0] and TXD[1:], because the
REF_CLK frequency is 10 times faster than the data rate of the 10Mbps.
SNI Interface
The IP101A LF also provides serial-network interface for legacy MACs, when the chip operates at
10BASE-T either by Auto-Negotiation resolved result or by forced mode. To setup for this mode of
operation, pull both the MII/SNIB and the COL/RMII pins to low.
The transaction protocol of SNI interface is almost identical to that of MII interface, except of data bit width
and clock rate. This interface consists of 10Mbps transmit and receive clock generated by PHY’s digital
phase-locked loop (DPLL), 10Mbps transmit and receive serial data, transmit enable, collision detect, and
carry sense signals.
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
