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IP101A LF
Data Sheet
Flexible Clock Source
Pin1
COL/RMII
Pin44
MII/SNIB
Function
1
1
RMII, ext 50MHz osc clk in to pin7
1
0
RMII, 25MHz crystal or osc from X1,X2; 50MHz clk out to pin16. (Please refer
to the following figure for our recommened application circuit.)
0
1
MII, 25MHz crystal or osc from X1,X2
0
0
SNI, 25MHz crystal or osc from X1,X2
While pin1=1 and pin44=0 has been selected, 50MHz clock will be provided by IP101A LF in RMII mode.
We suggest the application circuit as the following :
Buffer
IP101A
25M
Other PHY
CPU/Switch/MAC
Pin16
Pin7
Pin46
Pin47
50MHz colck
For this configuration, RMII reference clock for IP101A LF is from pin7. Clock skew could be eliminated by
adding an external buffer and placing equal trace lengths between buffer outputs and each chip.
Oct 22, 2007
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Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12