IP1000A LF
Preliminary Data Sheet
44/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
reaching 0xFFFFFFFF.
All IP1000A LF byte and octet count based
statistic registers include the VLAN tag (4 octets)
regardless of whether or not the IP1000A LF is
adding (on frame transmission) or removing (on
frame reception) the VLAN tag automatically.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
McstOctetXmtOk reaches a value of 0xC0000000.
McstOctetXmtOk is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the McstOctetXmtOk bit within the
StatisticsMask register.
3.2.1.22 MultiColFrames
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xEC
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
MultiColFrames
Multiple Collision Frames is a count of the number
of frames that are involved in more than one
collision
and
are
subsequently
transmitted
successfully. MultiColFrames will wrap around to
zero after reaching 0xFFFFFFFF. See IEEE 802.3
Clause 30.3.1.1.4.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
MultiColFrames reaches a value of 0xC0000000.
MultiColFrames is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the MultiColFrames bit within the
StatisticsMask register.
R/W
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