IP1726 LF
Preliminary Data Sheet
8/33
Jun 15, 2005
Copyright © 2003, IC Plus Corp.
IP1726 LF-DS-R06
67
REG18
O
1.8V regulator control. This pin can be connected to the
base of the PNP transistor to generate the 1.8V power.
Pin description (continued)
Pin No.
Label
Type
Description
Power & Ground
68
VDDPLL
P
1.8V Power for PLL
69
GNDPLL
P
Ground for PLL
4,37,57,80,114 VDD18
P
1.8V Power for Core circuit
3,38,58,81,113 GND18
P
Ground for core circuit
2,23,39,52,66,
83,101,115
VDD33
P
3.3/1.8V Power for I/O PAD
1,24,40,51,65,
82,102,116
GND33
P
Ground for I/O PAD
Power On setting. These pins’ state will be latched upon reset
117
1st MII_Force_Link
IL, PU This pin is pulled up internally. Connecting a pull down
resistor to this pin will force the 1st MII linking to the
external device regardless of the PHY polling status,
119
2nd MII_Force_Link
IL, PU This pin is pulled up internally. Connecting a pull down
resistor to this pin will force the 2nd MII linking to the
external device regardless of the PHY polling status,
121
IO_SLEW
IL, PD Output PAD slew rate setting. 1: fast, 0: normal (Default)
128, 123
IO_DRIVE[1:0]
IL, PD Output PAD driving current capability
00 : 4mA (Default)
01 : 8mA
10 : 12mA
11 : 16mA
7
P25_LINK_CPU
IL, PD 1st MII (port 25) linked to CPU.
1: 1st MII is connected to CPU.
0: 1st MII is the normal port (Default)
9
P26_LINK_CPU
IL, PD 2nd MII (port 26) linked to CPU.
1:2nd MII is connected to CPU.
0: 2nd MII is the normal port (Default)
11
P25_REV_MII
IL, PD 1st MII (port 25) is reverse MII interface
1: Reverse MII; 0:Normal MII (Default).
15
P26_REV_MII
IL, PD 2nd MII (port 26) is reverse MII interface.
1: Reverse MII; 0:Normal MII (Default).
19,17
TEST_MODE[1:0]
IL, PD Reserved for IC test.
21
IPG_COMP_EN
IL, PD Transmit IPG compensation (+80ppm)
1: Enable; 0: Disable (Default)
28
FCTRL_OFF
IL, PD Disable the full duplex flow control of all ports
1: Disable; 0: Enable (Default)
31
BKP_OFF
IL, PD Disable the half duplex backpressure control of all ports.
1: Disable; 0: Enable (Default).
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