IP1000A LF
Preliminary Data Sheet
28/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.1.10
1000BASE-T Control Register (Reg9)
Class............................. PHY Registers
Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers
Register Address .......... 0x9
Default .......................... 0x0
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
9.7:0
Reserved
Ignore when read
R/W
Reserved to
0x00
9.8
1000BASE-T Half
Duplex
1 = Advertise
0 = Not advertise
R/W
0
0
9.9
1000BASE-T Full
Duplex
1 = Advertise
0 = Not advertise
R/W
0
0
9.10
Port Type
1 = Prefer multi-port device (MASTER)
0 = Prefer single-port device (SLAVE)
R/W
0
0
9.11
Configuration
Value
1 = Manual configure as MASTER
0 = Manual configure as SLAVE
R/W
0
0
9.12
Manual
Configuration
Enable
1 = Manual Configuration Enable
0 = Automatic Configuration
R/W
0
0
9.15:13 Test mode
000 = Normal Mode
001 = Test Mode 1 - Transmit waveform Test
010 = Test Mode 2 - Transmit Jitter Test (MASTER
mode)
011 = Test Mode 3 - Transmit Jitter Test (SLAVE
mode)
100 = Test Mode 4 - Transmit Distortion Test
101, 110, 111 = Reserved
R/W
000
000
3.1.11
1000BASE-T Status Register (Reg10)
Class............................. PHY Registers
Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers
Register Address .......... 0xA
Default .......................... 0x0
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
10.7:0 Idle Error Count
RO
0x00
0x00
10.8
Reserved
Ignore when read
RO
Reserved to 0
10.9
Reserved
Ignore when read
RO
Reserved to 0
10.10
Link Partner
1000BASE-T Half
Duplex Capability
1 = Link Partner is capable of 1000BASE-T half
duplex
0 = Link Partner is not capable of 1000BASE-T
half duplex
RO
0
0
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