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IP1000ALF-DS-R04 数据表(PDF) 49 Page - List of Unclassifed Manufacturers

部件名 IP1000ALF-DS-R04
功能描述  Gigabit Ethernet NIC Single Chip
PDF  75 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
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标志 ETC2 - List of Unclassifed Manufacturers

IP1000ALF-DS-R04 数据表(HTML) 49 Page - List of Unclassifed Manufacturers

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IP1000A LF
Preliminary Data Sheet
49/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
5
VGAPaletteSnoop VGA Palette Snoop. VGAPaletteSnoop controls
how VGA compatible graphics devices handle
accesses
to
VGA
palette
registers.
When
VGAPaletteSnoop is a logic 1, palette snooping is
enabled (i.e., the device does not respond to
palette reg-ister writes and snoops the data).
When VGAPaletteSnoop is a logic 0, the device
should treat palette write accesses like all other
accesses.
R
6
ParityErrorResponse Parity Error Response. When ParityErrorResponse
is a logic 1 the IP1000A LF responds to parity
errors as defined within the PCI specification.
When ParityErrorResponse is a logic 0, the
IP1000A LF ignores parity errors.
R/W
7
SteppingControl
Stepping Control. SteppingControl determines
whether or not a device does address/data
stepping. Devices that never do stepping must
hardwire SteppingControl to a logic 0. Devices
that
always
do
stepping
must
hardwire
SteppingControl to a logic 1.
R
8
SERREnable
System Error Enable. When SERREnable is a
logic 1, the SERRN signal is allowed to transition
as appropriate. When SERREnable is a logic 0,
the SERRN signal is a continuous logic 0.
R/W
9
FastBack-to-Back
Enable
Fast Back-to-Back Enable. FastBack-to-BackEnable
controls whether or not a master can do fast
back-to-back transactions to different devices.
Initialization software will set FastBack-to-Back-
Enable if all targets are fast back-to-back capable.
If Fast-Back-to-BackEnable is a logic 1, the master
is allowed to generate fast back-to-back transactions
to different agents. If FastBack-to-BackEnable is a
logic 0, fast back-to-back transactions are only
allowed to the same agent.
R
10
InterruptDisable
Interrupt Disable. InterruptDisable disables the
IP1000A
LF
from
asserting
INTAN.
If
InterruptDisable is a logic 0, the IP1000A LF may
assert the INTAN signal. If InterruptDisable is a
logic 1, the IP1000A LF may not assert the INTAN
signal.
R/W
15..11 Reserved
Reserved for future use. Write as zero, ignore on read.
N/A



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