IP1000A LF
Preliminary Data Sheet
38/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.12 FramesXmtdOk
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xDC
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
FramesXmtdOk
Frames Transmitted OK is a count of the number
of frames that are successfully transmitted.
FramesXmtdOk will wrap around to zero after
reaching 0xFFFFFFFF. See IEEE 802.3 Clause
30.3.1.1.2.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FramesXmtdOk reaches a value of 0xC0000000.
FramesXmtdOk is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl register,
and a logic 0 to the FramesXmtdOk bit within the
StatisticsMask register.
R/W
3.2.1.13 FrameTooLongErrors
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xC8
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
FrameTooLong-
Errors
Frame Too Long Errors is a count of frames
received whose length exceed the value in the
MaxFrameSize register. FrameTooLongErrors will
wrap around to zero after reaching 0xFFFF. See
IEEE 802.3 Clause 30.3.1.1.25.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
FrameTooLongErrors reaches a value of 0xC000.
FrameTooLongErrors is enabled by writing a logic
1 to the StatisticsEnable bit in the MACCtrl
register, and a logic 0 to the FrameTooLongErrors
bit within the StatisticsMask register.
R/W
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