IP1000A LF
Preliminary Data Sheet
41/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.1.17 MacControlFramesXmtd
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xFA
Default Value ................ 0x0000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
15..0
MacControl-
FramesXmtd
MAC Control Frames Transmitted is the count of
MAC control frames transmitted by the IP1000A
LF. Note, acControl-FramesXmtd does not include
MAC control frames transferred to the IP1000A LF
by the host system via the transmit DMA process.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
MacControlFramesXmtd
reaches
a
value
of
0xC000. MacControlFramesXmtd is enabled by
writing a logic 1 to the StatisticsEnable bit in the
MACCtrl
register,
and
a
logic
0
to
the
MacControlFramesXmtd
bit
within
the
StatisticsMask register.
R/W
3.2.1.18 McstFramesRcvdOk
Class............................. Ethernet MIB Statistics
I/O Base Address ......... IoBaseAddress register value
Memory Base Address . MemBaseAddress register value
Address Offset .............. 0xB8
Default Value ................ 0x00000000
Access Rule.................. Double Word
Width ............................ 32 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
31..0
McstFramesRcvd
Ok
Broadcast Frames Received OK is the count of the
number of frames that are successfully received to a
group destination address other than the broadcast
address (0xFFFFFFFFFFFF). McstFramesRcvdOk
does not include frames received with frames too
long, FCS, length or alignment errors, or frames lost
due to internal MAC sublayer error (i.e. overrun).
McstFramesRcvdOk will wrap around to zero after
reaching 0xFFFFFFFF. See IEEE 802.3 Clause
30.3.1.1.21.
An UpdateStats interrupt (UpdateStats bit within
the
IntStatus
register)
will
occur
when
McstFramesRcvdOk
reaches
a
value
of
0xC0000000. McstFramesRcvdOk is enabled by
writing a logic 1 to the StatisticsEnable bit in the
R/W
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