IP1000A LF
Preliminary Data Sheet
55/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
0
IoBaseAddrInd
I/O Base Address Indicator. When IoBaseAddrInd
is a logic 1, IoBaseAddress contains the valid I/O
base address for the IP1000A LF.
R/W
7..1
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
31..8
IoBaseAddress
I/O Base Address. IoBaseAddress contains the 24
bit I/O base address value. With 24 bits, the
IP1000A LF uses 256 bytes of I/O address space.
R/W
3.2.2.14 LatencyTimer
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x0D
Default Value ................ 0x00
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
2..0
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
7..3
LatencyTimer
Latency
Timer.
LatencyTimer
indicates,
in
increments of 8 bus clocks, the length of time
which the IP1000A LF may hold the PCI bus in the
presence of other bus requestors. Whenever the
IP1000A LF asserts the FRAMEN signal, the
latency timer is started. When the latency timer
count expires, the IP1000A LF must relinquish the
bus as soon as its GNTN signal has been
de-asserted.
R/W
3.2.2.15 MaxLat
Class............................. PCI Configuration Registers, Configuration
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x3F
Default Value ................ 0x0A
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
MaxLat
Maximum Latency. MaxLat specifies, in 250 ns
increments, how often the IP1000A LF requires
bus access while operating as a bus master. Bits
5 through 1 of the MaxLat value are loaded from
the ConfigParm field within an EEPROM during
auto initialization of the IP1000A LF.
R
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