69 / 75 page
IP1000A LF
Preliminary Data Sheet
69/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
tCL
1
Clock Low Time
18
ns
Clock Slew Rate
2 (peak to peak)
0.1
V/ns
tSLCH
S Active Setup Time (relative to C)
10
ns
tCHSL
S Not Active Hold Time (relative to C)
10
ns
tDVCH
Data In Setup Time
5
ns
tCHDX
Data In Hold Time
5
ns
tCHSH
S Active Hold Time (relative to C)
10
ns
tSHCH
S Not Active Setup Time (relative to C)
10
ns
tSHSL
S Deselect Time
100
ns
tSHQZ
2
Output Disable Time
15
ns
tCLQV
Clock Low to Output Valid
15
ns
tCLQX
Output Hold Time
0
ns
tHLCH
HOLD Setup Time (relative to C)
10
ns
tCHHH
HOLD Hold Time (relative to C)
10
ns
tHHCH
HOLD Setup Time (relative to C)
10
ns
tCHHL
HOLD Hold Time (relative to C)
10
ns
tHHQX
2
HOLD to Output Low-Z
15
ns
tHLQZ
2
HOLD to Output High-Z
20
ns
tDP
2
S High to Deep Power-down Mode
3
µs
tRES1
2
S High to Standby Mode without
Electronic Signature Read
3
µs
tRES2
2
S High to Standby Mode with
Electronic Signature Read
1.8
µs
tW
Write Status Register Cycle Time
5
15
ms
tPP
Page Program Cycle Time
2
5
ms
tSE
Sector Erase Cycle Time
2
3
s
tBE
Bulk Erase Cycle Time
3
6
s
EEPROM Interface
Tskc
EESK cycle
1
µs
-
ns
Tskh
EESK high
250
-
ns
Tskl
EESK low
250
-
ns
Tcs
EECS low
250
-
ns
Tpd
EEDI valid wrt EESK rise
100
-
ns
Tcsk
EECS setup wrt EESK rise
50
-
ns
Tcsh
EECS hold wrt EESK fall
0
-
ns
Tdos
EEDO setup wrt EESK rise
70
500
ns
Tdoh
EEDO hold wrt EESK rise
-
500
ns
MII Interface (10/100) – Transmit
Tcc
TXCLK cycle
T=1 when 100Mb/s;
10 when 10Mb/s
40T
ns
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