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IP175A LF
Preliminary Data Sheet
5.3.6
EEPROM Timing
a.
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Receive clock period
-
20480
-
ns
TsSCL
SDA to SCL setup time
2
-
-
ns
ThSCL
SDA to SCL hold time
0.5
-
-
ns
R ead data cycle
SC L
SD A
T sSCL
T hSCL
T SCL
b.
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Transmit clock period
-
20480
-
ns
TdSCL
SCL falling edge to SDA
-
-
5200
ns
Com and cycle
TdSCL
SCL
SDA
TSCL
6
Order Information
Part No.
Package
Notice
IP175A
128-PIN QFP
-
IP175A LF
128-PIN QFP
Lead free
59/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08