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IP178C/IP178C LF/IP178CH/IP178CH LF
Datasheet
3.3.5
EEPROM Timing
a.
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Receive clock period
-
20480
-
ns
TsSCL
SDA to SCL setup time
2
-
-
ns
ThSCL
SDA to SCL hold time
0.5
-
-
ns
R ead data cycle
SC L
SD A
T sSCL
T hSCL
T SCL
b.
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June 21, 2007
Copyright © 2004, IC Plus Corp.
IP178Cx-DS-R12
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Transmit clock period
-
20480
-
ns
TdSCL
SCL falling edge to SDA
-
-
5200
ns
Com and cycle
TdSCL
SCL
SDA
TSCL
3.4
Thermal Data
Theta Ja
Theta Jc
Conditions
Units
29.1~30.4
9.3~10.7
2 Layer PCB
oC/W