109 / 111 page

IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.7
EEPROM Timing
a.
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Receive clock period
-
20480
-
ns
TsSCL
SDA to SCL setup time
2
-
-
ns
ThSCL
SDA to SCL hold time
0.5
-
-
ns
R ead data cycle
SC L
SD A
T sSCL
T hSCL
T SCL
b.
Symbol
Description
Min.
Typ.
Max.
Unit
TSCL
Transmit clock period
-
20480
-
ns
TdSCL
SCL falling edge to SDA
-
-
5200
ns
Com and cycle
TdSCL
SCL
SDA
TSCL
3.4
Thermal Data
Theta Ja
Theta Jc
Conditions
Units
38.2
--
2 Layer PCB
oC/W
Mar 09, 2007
109/111
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14