3 Pin Configuration and Functions

A

B

GND

QE

CLR

CLK

QA

QB

QC

QD

VCC

QH

QG

QF

Figure 3-1. CD54AC(T)164 J Package; 14-Pin CDIP;

CD74AC(T)164 D, N, or PW Package; 14-Pin SOIC,

PDIP, or TSSOP (Top View)

B

Q

A

Q

B

Q

C

Q

D

GND

Q

H

Q

G

Q

F

Q

E

CLR

CLK

PAD

A

V

CC

2

3

4

5

6

7

13

12

11

10

9

8

1

14

Figure 3-2. CD74AC(T)164 BQA Package; 14-Pin

WQFN (Top View)

Table 3-1. Pin Functions

PIN

TYPE1

DESCRIPTION

NAME

NO.

A

1

I

Gated serial input A

B

2

I

Gated serial input B

QA

3

O

Parallel output A

QB

4

O

Parallel output B

QC

5

O

Parallel output C

QD

6

O

Parallel output D

GND

7

G

Ground

CLK

8

I

Clock input, rising edge triggered

CLR

9

I

Asynchronous register clear input, active low

QE

10

O

Parallel output E

Q F

11

O

Parallel output F

QG

12

O

Parallel output G

QH

13

O

Parallel output H

VCC

14

P

Positive supply

Thermal pad2

—

The thermal pad can be connect to GND or left floating. Do not connect to any other signal or supply.

1. Signal Types: I = Input, O = Output, P = Power, G = Ground.

2. BQA package only.

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CD54AC164, CD74AC164, CD54ACT164, CD74ACT164

SCHS240D – NOVEMBER 1998 – REVISED OCTOBER 2024

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