6 Detailed Description

6.1 Overview

The CDx4AC(T)164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as

well as an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data

line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK

is high or low, provided that the minimum set-up time requirements are met.

The CLK pin of the CDx4AC(T)164 is rising-edge triggered, activating on the transition from LOW to HIGH. Upon

a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and

propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each

clock trigger. If a low signal is applied to the CLR pin, then the CDx4AC(T)164 will set all registers to a logical

low value immediately.

6.2 Functional Block Diagram

CLR

A

CLK

D

R

Q

5 Additional

Shift Register

Stages

B

D

R

Q

QH

QG

QF

QE

QD

QC

QB

QA

D

R

Q

Figure 6-1. Logic Diagram (Positive Logic) for CDx4AC(T)164

6.3 Feature Description

6.3.1 Standard CMOS Inputs

This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically

modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst

case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the

maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).

Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined

by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this

specification will result in excessive power consumption and could cause oscillations. More details can be found

in Implications of Slow or Floating CMOS Inputs.

Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at

VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can

be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a

10kΩ resistor, however, is recommended and will typically meet all requirements.

6.3.2 TTL-Compatible CMOS Inputs

This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL

logic devices by having a reduced input voltage threshold.

TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with

the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the

maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given

in the Electrical Characteristics, using Ohm's law (R = V ÷ I).

TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined

by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this

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CD54AC164, CD74AC164, CD54ACT164, CD74ACT164

SCHS240D – NOVEMBER 1998 – REVISED OCTOBER 2024

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Product Folder Links: CD54AC164 CD74AC164 CD54ACT164 CD74ACT164