GND

DA4

N

DA4

P

DB4

N

DB4

P

DA3

N

DA3

P

NC

NC

DB3

N

DB3

P

DB2

N

DB2

P

DA2

N

DA2

P

DB1

N

DB1

P

DA1

N

DA1

P

CLK

AN

CLK

AP

CLK

BN

CLK

BP

D2N

D2P

/OE

SEL

D1N

D1P

D4N

D4P

D3N

D3P

CLK

N

CLK

P

C

VDD

C

VIA to

ground plane

VIA to

power plane

To MIPI

Modules

To MIPI Port

To Control

Logic

22

TS5MP645

SCDS385B – JANUARY 2018 – REVISED JULY 2018

www.ti.com

Product Folder Links: TS5MP645

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Copyright © 2018, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

Place the supply de-coupling capacitors as close to the VDD and GND pin as possible. The spacing between the

power traces, supply and ground, and the signal I/O lines, clock and data, should be a minimum of three times

the race width of the signal I/O lines to maintain signal integrity.

The characteristic impedance of the trace(s) must match that of the receiver and transmitter to maintain signal

integrity. Route the high-speed traces using a minimum amount of vias and corners. This will reduce the amount

of impedance changes.

When it becomes necessary to make the traces turn 90°, use two 45° turns or an arc instead of making a single

90° turn.

Do not route high-speed traces near crystals, oscillators, external clock signals, switching regulators, mounting

holes or magnetic devices.

Avoid stubs on the signal lines.

All I/O signal traces should be routed over a continuous ground plane with no interruptions. The minimum width

from the edge of the trace to any break in the ground plane must be 3 times the trace width. When routing on

PCB inner signal layers, the high speed traces should be between two ground planes and maintain characteristic

impedance.

High speed signal traces must be length matched as much as possible to minimize skew between data and clock

lines.

11.2 Layout Example

Figure 26. Layout Example