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BQ20Z40-R1PW 数据表(PDF) 2 Page - Texas Instruments

部件名 BQ20Z40-R1PW
功能描述  SBS 1.1-COMPLIANT GAS GAUGE ENABLED WITH IMPEDANCE TRACK™ TECHNOLOGY FOR USE WITH THE bq29330
PDF  22 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

BQ20Z40-R1PW 数据表(HTML) 2 Page - Texas Instruments

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bq20z40-R1
SLUS993A
– DECEMBER 2009 – REVISED MARCH 2011
www.ti.com
THERMAL INFORMATION
bq20z40-R1
THERMAL METRIC(1)
TSSOP (PW)
QFN (RSM)
UNITS
20 PINS
32 PINS
θJA, High K
Junction-to-ambient thermal
89.5
37.4
resistance(2)
θJC (top)
Junction-to-case(top) thermal
23.4
30.6
resistance(3)
θJB
Junction-to-board thermal
41.0
7.7
resistance(4)
°C/W
ψJT
Junction-to-top characterization
0.9
0.4
parameter(5)
ψJB
Junction-to-board characterization
40.5
7.5
parameter(6)
θJC (bottom)
Junction-to-case(bottom) thermal
n/a
2.6
resistance(7)
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
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© 2009–2011, Texas Instruments Incorporated
Product Folder Link(s) :bq20z40-R1
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