PIC16LF18326 datasheet(26/471 Pages) MICROCHIP

26 / 471 page

PIC16(L)F18325/18345

DS40001795C-page 26

Preliminary

 2015-2016 Microchip Technology Inc.

3.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 8.5 “Automatic Context Saving”

for more information.

3.2

16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or

Underflow will set the appropriate bit (STKOVF or

STKUNF) in the PCON0 register, and if enabled, will

cause a software Reset. See Section 4.4 “Stack” for

more details.

3.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers, program memory, and data

EEPROM, which allows one Data Pointer for all

memory. When an FSR points to program memory,

there is one additional instruction cycle in instructions

using INDF to allow the data to be fetched. General

purpose memory can now also be addressed linearly,

providing the ability to access contiguous data larger

than

bytes.

See

Section 4.5

“Indirect

Addressing”

for more details.

3.4

Instruction Set

There are 48 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 34.0 “Instruction Set Summary”

for more

details.

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