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PIC16LF18326 数据表(PDF) 5 Page - Microchip Technology |
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PIC16LF18326 数据表(HTML) 5 Page - Microchip Technology |
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5 / 471 page  Pin Allocation Tables TABLE 1: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18325) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — — — — — SS2(1) — — — IOC Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF+ C1IN0- C2IN0- —DAC1REF+ — ——— — — — — — IOC Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) — CWG1IN(1) CWG2IN(1) — — — — INT(1) IOC Y — RA3 4 3 — — — — — — ——— — — — — — IOC Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) SOSCO — — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 ANA5 — —— — — T1CKI(1) SOSCIN SOSCI —— — — — CLCIN3(1) — IOC Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) SCL1(1,3,4) — — — IOC Y — RC1 9 8 ANC1 — C1IN1- C2IN1- —— — — CCP4(1) —— SDI1(1) SDA1(1,3,4) — CLCIN2(1) — IOC Y — RC2 8 7 ANC2 — C1IN2- C2IN2- — — MDCIN1(1) — — — — — — — — IOC Y — RC3 7 6 ANC3 — C1IN3- C2IN3- —— MDMIN(1) T5G(1) CCP2(1) — — SS1(1) — CLCIN0(1) — IOC Y— RC4 6 5 ANC4 — — — — — T3G(1) — — — SCK2(1) SCL2(1,3,4) — CLCIN1(1) — IOC Y — RC5 5 4 ANC5 — — — —MDCIN2(1) T3CKI(1) CCP1(1) —— SDI2(1) SDA2(1,3,4) RX(1) —— IOC Y — VDD 1 16 — — — — — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — — — — — VSS Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 4: These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ ST as selected by the INLVL register. |
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