±1.0

±0.8

±0.6

±0.4

±0.2

0.0

0.2

0.4

0.6

0.8

1.0

±20

±15

±10

±5

0

5

10

15

20

ADC Differential Peak-to-Peak Input (V)

C030

29

MUX506, MUX507

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SBAS803A – NOVEMBER 2016 – REVISED NOVEMBER 2017

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Typical Application (continued)

9.2.2 Detailed Design Procedure

The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system

for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 42. The

circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output

buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple

channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog

circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal

input signal at each input channel. Detailed design considerations and component selection procedure can be

found in the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for

High-Voltage Inputs with Lowest Distortion.

9.2.3 Application Curve

Figure 43. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block