Timing diagrams

STP16DP05

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Timing diagrams

Note:

OUTn = ON when Dn = H OUTn = OFF when Dn = L

Figure 7.

Timing diagram

Note:

The latches circuit holds data when the LE\DM1 terminal is Low.

1

When LE\DM1 terminal is at High level, latch circuit hold the data it passes from the input to

the output.

2

When OE\DM2 terminal is at Low level, output terminals OUT0 to OUT15 respond to the

data, either ON or OFF.

3

When OE\DM2 terminal is at High level, it switches off all the data on the output terminal.

Table 9.

Truth table

CLOCK

LE\DM1

OE\DM2

SERIAL-IN

OUT0 ............. OUT7 ................ OUT15

SDO

H

L

Dn

Dn ..... Dn - 7 ..... Dn -15

Dn - 15

L

L

Dn + 1

No Change

Dn - 14

H

L

Dn + 2

Dn + 2 ..... Dn - 5 ..... Dn -13

Dn - 13

X

L

Dn + 3

Dn + 2 ..... Dn - 5 ..... Dn -13

Dn - 13

X

H

Dn + 3

OFF

Dn - 13

OE\DM2

LE\DM1