MCU

VCC

10 k

GPIO Output

CLK

CLK/2

Q

D

2

1

3

4

5

CLK

SN74LVC1G80

12

SN74LVC1G80

SCES221S – APRIL 1999 – REVISED NOVEMBER 2016

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Copyright © 1999–2016, Texas Instruments Incorporated

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

A useful application for the SN74LVC1G80 is using it as a frequency divider. By feeding back the output (Q) to

the input (D), the output will toggle on every rising edge of the clock waveform. In other words, the output goes

HIGH once every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two.

The SN74LVC1G80 does not have preset or clear functions so the initial state of the output is unknown. This

application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW.

Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high

impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor

the clock division.

9.2 Typical Application

Figure 5. Clock Frequency Division

9.2.1 Design Requirements

For this application a resistor needs to be placed on the feedback line in order for the initialization voltage from

the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be

challenged by the GPIO from the microcontroller and from the output of the SN74LVC1G80.

The SN74LVC1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus

contention because it can drive currents that would exceed maximum limits.

9.2.2 Detailed Design Procedure

1. Recommended input conditions:

–

For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.

–

For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.

–

Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See

Recommended Operating Conditions.

2. Recommended output conditions:

–

Load currents should not exceed ±50 mA. See Absolute Maximum Ratings .

–

Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See

Recommended Operating Conditions.