GVDD (+12 V)

VDD (+12 V)

PVDD

PVDD

GVDD (+12 V)

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

TAS5508/18

PWM1_P

PWM1_M

VALID

Microcontroller

I2C

10 µH

10 µH

100 nF

TAS5352ADDV

GVDD_B

OTW

SD

PWM_A

RESET_AB

PWM_B

OC_ADJ

GND

AGND

VREG

M3

M2

M1

PWM_C

RESET_CD

PWM_D

GVDD_C

GVDD_D

BST_D

PVDD_D

OUT_D

GND_D

GND_C

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND_B

GND_A

VDD

GVDD_A

BST_A

PVDD_A

OUT_A

NC

NC

NC

NC

NC

PVDD_D

PVDD_A

NC

25 V

33 nF

100 nF

50 V

100 nF

1 µF

100 nF

50 V

10 µH

470 µF

50 V

470 F

µ

50 V

33 nF 25 V

3.3 W

100 nF

0 W

22 k

100 nF

33 nF 25 V

100 nF

50 V

10 nF

50 V

100 nF

100 nF

100 nF

50 V

33 nF

25V

100 nF

50 V

100 nF

10 µH

3.3 W

10 nF

50 V

10 nF

50 V

3.3 W

1 nF

50 V

1 nF

50 V

3.3 W

10 nF

50 V

2.2 W

2.2 W

2.2 W

2.2 W

1R

Copyright © 2016, Texas Instruments Incorporated

22

TAS5352A

SLES239A – NOVEMBER 2008 – REVISED DECEMBER 2016

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Copyright © 2008–2016, Texas Instruments Incorporated

8.2.3.1 Design Requirements

Table 8 lists the design requirements for this example.

Table 8. Design Requirements for Typical SE

DESIGN PARAMETER

EXAMPLE

Low Power (Pullup) Supply

3.3 V

Mid Power Supply (GVDD, VDD)

12 V

High Power Supply (PVDD)

12 – 36 V

PWM Inputs

INPUT A = 0 – 3.3 V PWM

INPUT_B = 0 – 3.3 V PWM

INPUT_C = 0 – 3.3 V PWM

INPUT_D = 0 – 3.3 V PWM

Speaker Impedance

3 – 4

Ω

8.2.3.2 Application Curves

Relevant performance plots for TAS5352A in SE configuration are shown in SE Configuration.

Table 9. Relevant Performance Plots, SE Configuration

PLOT TITLE

FIGURE NUMBER

Total Harmonic Distortion + Noise vs. Output Power

Figure 8

Output Power vs. Supply Voltage

Figure 9

Power Output vs. Case Temperature

Figure 10

8.2.4 PBTL Application With AD Modulation Filters

Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters