TCA8418EYFPR datasheet(29/51 Pages) TI2

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TCA8418E

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SCPS222C – MAY 2010 – REVISED OCTOBER 2015

8.6.2.1 Configuration Register (Address 0x01)

Table 10. Configuration Register Field Descriptions

BIT

NAME

DESCRIPTION

Auto-increment for read and write operations; See below table for more information

0 = disabled

1 = enabled

GPI event mode configuration

GPI_E_CFG

0 = GPI events are tracked when keypad is locked

1 = GPI events are not tracked when keypad is locked

Overflow mode

OVR_FLOW_M

0 = disabled; Overflow data is lost

1 = enabled; Overflow data shifts with last event pushing first event out

Interrupt configuration

0 = processor interrupt remains asserted (or low) if host tries to clear interrupt while there is

INT_CFG

still a pending key press, key release or GPI interrupt

1 = processor interrupt is deasserted for 50

μs and reassert with pending interrupts

Overflow interrupt enable

OVR_FLOW_IEN

0 = disabled; INT is not asserted if the FIFO overflows

1 = enabled; INT becomes asserted if the FIFO overflows

Keypad lock interrupt enable

K_LCK_IEN

0 = disabled; INT is not asserted after a correct unlock key sequence

1 = enabled; INT becomes asserted after a correct unlock key sequence

GPI interrupt enable to host processor

GPI_IEN

0 = disabled; INT is not asserted for a change on a GPI

1 = enabled; INT becomes asserted for a change on a GPI

Key events interrupt enable to host processor

KE_IEN

0 = disabled; INT is not asserted when a key event occurs

1 = enabled; INT becomes asserted when a key event occurs

Bit 7 in this register is used to determine the programming mode. If it is low, all data bytes are written to the

incremented after each byte is written, and the next data byte is stored in the corresponding register. Registers

are written in the sequence shown in Table 9. Once the GPIO_PULL3 register (0x2E) is written to, the command

byte returns to register 0. Registers 0 and 2F are reserved and a command byte that references these registers

is not acknowledged by the TCA8418E.

The keypad lock interrupt enable determines if the interrupt pin is asserted when the key lock interrupt (see

Interrupt Status Register) bit is set.

8.6.2.2 Interrupt Status Register, INT_STAT (Address 0x02)

Table 11. Interrupt Status Register Field Descriptions

BIT

NAME

DESCRIPTION

N/A

Always 0

N/A

Always 0

N/A

Always 0

CTRL-ALT-DEL key sequence status. Requires writing a 1 to clear interrupts.

CAD_INT

0 = interrupt not detected

1 = interrupt detected

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