TCA8418E

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SCPS222C – MAY 2010 – REVISED OCTOBER 2015

6.7 Reset Timing Requirements for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I

2C Bus

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)

MIN

MAX

UNIT

tW

Reset pulse duration

120(1)

μs

tREC

Reset recovery time

120(1)

μs

tRESET

Time to reset

120(1)

μs

(1)

The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the

same clock signal, presumably free-running, with a nominal period of 50

μs. When an input changes state, the new state is clocked into

the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked

state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,

it will take anywhere from zero to 50

μs after the input transition to clock the signal into the first stage. Therefore, the total debounce

time may be as long as 100

μs. Finally, to account for a slow clock, the spec further guard-banded at 120 μs.

6.8 Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I

2C Bus

PARAMETER

FROM

TO

MIN

MAX

UNIT

Key event or Key

20

60

unlock or Overflow

GPI_INT with

INT

40

120

ROW0–7,

Debounce_DIS_Low

tIV

Interrupt valid time

μs

COL0–9

GPI_INT with

10

30

Debounce_DIS_High

CAD_INT

INT, CAD_INT

20

60

SCL

INT

tIR

Interrupt reset delay time

200

ns

SCL

CAD_INT

ROW0–7,

tPV

Output data valid

SCL

400

ns

COL0–9

tPS

Input data setup time

P port

SCL

0

ns

tPH

Input data hold time

P port

SCL

300

ns

6.9 Keypad Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I

2C

Bus

PARAMETER

MIN

MAX

UNIT

Key press to detection delay

25

μs

Key release to detection delay

25

μs

Keypad unlock timer

7

s

Keypad interrupt mask timer

31

s

Debounce

60

ms

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