PRMD2

50 V, 100 mA NPN/PNP Resistor-Equipped double

Transistors (RET)

14 June 2017

Product data sheet

1. General description

NPN/PNP Resistor-Equipped double Transistors (RET) in a leadless ultra small DFN1412-6

(SOT1268) Surface-Mounted Device (SMD) plastic package.

2. Features and benefits

• 100 mA output current capability

• Built-in bias resistors

• Simplifies circuit design

• Reduces component count

• Reduces pick and place costs

• Low package height of 0.5 mm

• AEC-Q101 qualified

3. Applications

• Digital applications

• Cost-saving alternative to BC847/BC857 series in digital applications

• Control of IC inputs

• Switching loads

4. Quick reference data

Table 1. Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Per transistor, for the PNP transistor with negative polarity

VCEO

collector-emitter

voltage

open base

-

-

50

V

IO

output current

-

-

100

mA

hFE

DC current gain

VCE = 5 V; IC = 5 mA; Tamb = 25 °C

60

-

-

R1

bias resistor 1

[1]

15.4

22

28.6

kΩ

R2/R1

bias resistor ratio

[1]

0.8

1

1.2

[1] See section "Test information" for resistor calculation and test conditions.