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TPS79101DBVT 数据表(PDF) 13 Page - Texas Instruments |
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TPS79101DBVT 数据表(HTML) 13 Page - Texas Instruments |
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13 / 30 page ![]() 7 3 10 R1 R2 C1 R1 R2 u u u OUT V R1 1 R2 VREF § · u ¨ ¸ © ¹ OUT R1 V VREF 1 R2 § · u ¨ ¸ © ¹ J A D JA T max T P max R T 13 TPS791 www.ti.com SLVS325D – MARCH 2001 – REVISED FEBRUARY 2018 Product Folder Links: TPS791 Submit Documentation Feedback Copyright © 2001–2018, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Power Dissipation and Junction Temperature Specified regulator operation is confirmed at a junction temperature of 125°C; restrict the maximum junction temperature to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: where • TJmax is the maximum allowable junction temperature • RθJA is the thermal resistance junction-to-ambient for the package (see the Thermal Information table) • TA is the ambient temperature (1) The regulator dissipation is calculated using: PD = (VIN – VOUT) × IOUT (2) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. 7.3.2 Programming the TPS79101 Adjustable Regulator The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider; see Figure 32. The output voltage is calculated using: where • VREF = 1.2246 V typ (the internal reference voltage) (3) Select resistors R1 and R2 for approximately a 50-µA divider current. Lower value resistors can be used for improved noise performance, but the solution consumes more power. Avoid higher resistor values because leakage current into or out of FB across R1, R2 creates an offset voltage that artificially increases or decreases the feedback voltage and thus erroneously decreases or increases VOUT. The recommended design procedure is to choose R2 = 30.1 k Ω to set the divider current at 50 µA, C1 = 15 pF for stability, and then calculate R1 using: (4) In order to improve the stability of the adjustable version, a small compensation capacitor is suggested to be placed between OUT and FB. For voltages < 1.8 V, the value of this capacitor must be 100 pF. For voltages > 1.8 V, the approximate value of this capacitor can be calculated as: (5) |
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