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MP2018 数据表(PDF) 9 Page - Monolithic Power Systems |
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MP2018 数据表(HTML) 9 Page - Monolithic Power Systems |
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9 / 13 page ![]() MP2018 – 16V, 500mA, LOW QUIESCENT CURRENT LINEAR REGULATOR MP2018 Rev. 1.0 www.MonolithicPower.com 9 7/12/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2018 MPS. All Rights Reserved. OPERATION The MP2018 is a linear regulator that supplies power to systems with high-voltage batteries. The MP2018 includes a wide 3V to 16V input range, low dropout voltage, and low quiescent supply current. Short-Circuit Protection (SCP) The regulator output current is limited internally, and the device is protected against short-circuit and overload conditions. The peak output current is limited to around 900mA, which exceeds the 500mA recommended continuous output current. Thermal Shutdown When the junction temperature exceeds the upper threshold (165°C), the thermal sensor sends a signal to the control logic to shut down the IC. The IC restarts when the temperature has cooled sufficiently (135°C). The maximum power output current is a function of the package’s maximum power dissipation for a given temperature. The maximum power dissipation depends on the thermal resistance of the case and the circuit board, the temperature difference between the die junction and the ambient air, and the rate of the air flow. GND and the exposed pad must be connected to the ground plane for proper dissipation. Power Good (PG) Output The MP2018 has a power good pin (PG). PG is the open drain of an internal MOSFET and should be connected to the output voltage (VOUT) or an external voltage source (<15V) through a resistor (i.e.: 100k Ω). If VOUT reaches 93% of the nominal value, the MOSFET turns off, and PG is pulled high by VOUT or an external voltage source. When VOUT drops to 88% of the nominal value, the PG voltage is pulled to GND. There is a delay time when PG asserts high. The delay time can be programmed by adding a capacitor on PGDL. Select a capacitor for PGDL using Equation (1): PGDL PGDL PGDL th_PGDL t (ms) I ( A) C (nF) V (V) (1) Where tPGDL is the desired delay time when PG asserts high, IPGDL is the PGDL charging current, and Vth_PGDL is 1.65V. Figure 2 shows the power good timing. |
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