MP2018

– 16V, 500mA, LOW QUIESCENT CURRENT LINEAR REGULATOR

MP2018 Rev. 1.0

www.MonolithicPower.com

11

7/12/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2018 MPS. All Rights Reserved.

APPLICATION INFORMATION

Selecting the Input Capacitor

For proper operation, place a dielectric type

X5R or X7R ceramic capacitor between 1 -

10µF (C1) between the input pin and ground.

Larger values in this range help improve line

transient response.

Selecting the Output Capacitor

For stable operation, use a dielectric type X5R

or X7R ceramic capacitor (C2) between 1 -

22µF. Larger values in this range help improve

load transient response and reduce noise.

Output capacitors of other dielectric types may

be used but are not recommended since their

capacitance can deviate greatly from their rated

value over temperature.

PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

good

regulation, ripple rejection, transient response,

and

thermal

performance.

It

is

highly

recommended to duplicate the EVB layout for

optimal performance. For best results, refer to

Figure 3, Figure 4, and follow the guidelines

below.

1.

Place the input and output bypass ceramic

capacitors

close

to

IN

and

OUT

respectively.

2.

Connect IN, OUT, and especially GND to a

large copper area to cool the chip and

improve thermal performance and long-

term reliability.

C2

C1

IN

PGDL

GND

PG

OUT

VIN

VOUT

MP2018

R1

C3

Figure 3: MP2018 Schematic

Top Layer

Bottom Layer

Figure 4: Recommended Layout

Design Example

Figure 5 shows a design example following the

application guidelines.

C2

C1

IN

PGDL

GND

PG

OUT

VIN

VOUT

MP2018

R1

C3

1μF

47nF

100kΩ

22μF

Figure 5: Design Example