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PFS7525L/H 数据表(PDF) 26 Page - Power Integrations, Inc. |
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PFS7525L/H 数据表(HTML) 26 Page - Power Integrations, Inc. |
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26 / 37 page ![]() Rev. D 04/25 26 PFS7523-7529/7533-7539 www.power.com Parameter Symbol Conditions SOURCE = 0 V; V CC = 12 V, -40 °C < T J(C) < 125 °C (Note C) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection (cont.) Normalized Frequency at Power Limit F LIM C REF = 1.0 µF T J(C) = 25 °C ±7 % 0 °C < T J(C) < 100 °C ±10 SOA Protection Fixed Off-Time t OFF(SOA) T J(C) = 25 °C 200 250 300 µ s Leading Edge Blanking (LEB) Time Period t LEB T J(C) = 25 °C See Note A 220 ns Minimum On-Time in IOCP t ON_OCP(MIN) T J(C) = 25 °C 400 ns VCC Auxiliary Power Supply VCC Operating Range VCC UVLO+ 12 15 V Start-Up VCC (Rising Edge) VCC UV(LO+) 0 °C < T J(C) < 100 °C 9.6 9.85 10.1 V Shutdown VCC (Falling Edge) VCC UV(LO-) 0 °C < T J(C) < 100 °C 9.05 9.3 9.55 V VCC Hysteresis VCC (HYS) 0 °C < T J(C) < 100 °C 0.50 0.57 0.65 V UVLO Shutdown Delay Timer t UV(LO-) See Note A 500 ns Time From VCC > VCC UVLO+ Until Device Commences Switching t RESET V > V BR+ See Note A 60 75 ms Series Regulator REFERENCE Pin Voltage V REF 0 °C < T J(C) < 100 °C 4.95 5.25 5.45 V REFERENCE Pin Required Capacitance C REF Full Power Mode 0.8 1.0 µ F Efficiency Mode 0.08 0.1 0.2 REFERENCE Pin UVLO Rising Edge REF UV+ 0 °C < T J(C) < 100 °C See Note A 5.0 V REFERENCE Pin UVLO Falling Edge REF UV- 0 °C < T J(C) < 100 °C See Note A 4.4 V Power Good Power Good Deasser- tion Threshold Output Reference Current I PG(T) 0 °C < T J(C) < 100 °C; VPGT = 3.0 V -10.65 -10 -9.35 µ A Power Good Delay Time (From FB > V PG+ to PG < 1 V) t PG 0 °C < T J(C) < 100 °C; PG = 20 kΩ Pull-Up to VCC, See Note A <15 µ s Power Good Deglitch Time t PG(D) See Note A 57 81 108 µ s |
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