PFS7526H datasheet(10/37 Pages) POWERINT

10 / 37 page

Rev. D 04/25

PFS7523-7529/7533-7539

www.power.com

Open FEEDBACK Pin Protection

The FEEDBACK pin continuously sinks a static current of I

FBPD [VCC >

VCC

UVLO+] to protect against a fault related to an open FEEDBACK pin

or incomplete feedback divider network. The internal current sink

introduces a small static offset to the output regulation which can be

accounted for in selecting the output feedback regulation components

(FEEDBACK pin divider).

Hysteretic Thermal Shutdown

The thermal shutdown circuitry senses the controller die temperature

which is well coupled to the heat sink through the exposed, grounded

pad. The threshold is set at 117 °C typical with a 36 °C hysteresis.

When the controller die temperature rises above this threshold (OTP),

the controller initiates a soft-shutdown and remains disabled until the

controller die temperature falls by ~36 °C, at which point the device

will re-initiate the start-up sequence.

The maximum time delay for soft-shutdown to occur after an OTP

event is detected is t

OTP beyond the next zero-crossing.

HiperPFS-3 Additional Features and Changes

Note: HiperPFS-3 is not a pin for pin drop-in replacement of

HiperPFS-2 due to functional changes and optimizations.

• Improved operating supply voltage maximum: 15 V.

• Reduced external component count.

• Improved tolerance of key parameters over a wide temperature

range.

• Modified architecture improving noise immunity and operational

accuracy.

• Feedback network voltage divider is decoupled from the loop

compensation components.

• High-line only family of parts added to HiperPFS-3 family.

• Peak-detector supports deglitch methodology for NTC in-rush

current limiting at start-up.

• Digital Power Factor Enhancer algorithm improves high-line light

load power factor.

• OTA error amplifier replaces voltage error amplifier of

HiperPFS-2.

• NLA implemented via fixed current sources for quick transient

response, replaces switched voltage gain in HiperPFS-2.

• Off-time controller senses actual feedback voltage to calculate

off-time to prevent inductor saturation.

• VOLTAGE MONITOR pin uses voltage-mode sensing rather than

current-mode sensing of HiperPFS-2, allowing flexibility in selection

of magnitude of resistor divider.

• Reduced minimum line feed-forward gain supports higher power

delivery during line sag events.

• Line feed-forward gain implemented with true squaring function,

versus piece-wise linear approximation.

• Line voltage functions performed in the digital domain: peak detec-

tion, feed-forward, brown-in/brown-out and PF-enhancement.

• Peak detector incorporates filtering to smooth out cycle-to-cycle

variation.

• Optimized brown-in/brown-out thresholds with tighter tolerances.

• Most timers are derived from an internal high-speed clock

providing accurate timing.

• eSIP-16 package pinout has been modified for optimal operation

and internal grounding.

• No-load/light-load power consumption optimized by re-engineered

burst-mode operation.

• Reduced control-engine power consumption: standby current

reduced by ~4~5× HiperPFS-2 nominal.

• HiperPFS-3 REFERENCE pin replaces HiperPFS-2 REFERENCE pin;

external bypass capacitor replaces external 1% resistor.

• V

FB(REF) reduced to 3.85 V nominal from 6.0 V nominal in

HiperPFS-2.

• Peak detector optimized across maximum operational conditions

when operating with distorted waveforms and line drop-outs.

• Square-wave detector feature for improved UPS operation.

• Power good function is independent of engine during operation

except for OTP events.

• FB

OFF fault check is always enabled during operation.

• Maximum CCM peak switching frequency has been increased from

~100 kHz to 123 kHz.

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