DIX4192 datasheet(21/71 Pages) TI2

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Ch2

Ch. 1

Ch2

Ch. 1

Ch2

BLS

(output)

SY C

(output)

CorU daa

(output)

Bit 0

Bit 1

Bit 2

Bit 4

Block Start

(Fr me

0St rtsHe

re)

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

JitterFrequency(Hz)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

100

SinusoidalJitterFrequency(Hz)

10k

100k

500m

200m

100m

50m

20m

10m

THD+N

OutputJitterAmplitude

InputJitterAmplitude

DIX4192

www.ti.com

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

Product Folder Links: DIX4192

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Feature Description (continued)

The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock

output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags

may be output at the general-purpose output (GPO) pins, or accessed through the status registers through the

SPI or I2C host interface. Refer to General-Purpose Digital Outputs and Control Registers for additional

information regarding the DIR status functions.

Figure 15. DIR Jitter Attenuation Characteristics

Figure 16. DIR Jitter Tolerance Plot

Figure 17. DIR Channel Status and User Data Serial Output Format Through the GPO Pins

DIX4192 数据表(PDF) 21 Page - Texas Instruments

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DIX4192 数据表(PDF) 21 Page - Texas Instruments

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