DIX4192 datasheet(12/71 Pages) TI2

12 / 71 page

Audio Serial

PortA

Audio Serial

PortB

Digital

Interface

Receiver(DIR)

Digital

Interface

Transmitter

(DIT)

TX+

TX-

SDINA

SDOUTA

LRCKA

BC A

SDINB

SDOUTB

LRCKB

BC B

CPM

CS or A0

CCLKorSCL

CDINor 1

CDOUT orSDA

INT

RST

Host

Interface

(SPIor I C)

and

Gene a

r l-

Purp s

o e

Outputs

Master

Cl ck

Distribution

MC K

RXCKI

FromRXCKO

GP 1

GP 2

GP 3

GP 4

AESOUT

RXCKO

LOCK

RX +

RX -

RX +

RX -

RX +

RX -

RX +

RX -

BLS

SY C

ControlandStatus

Registers

DIRCand U

DataBuffers

DITCand U

DataBuffers

DIX4192

Power

VDD18

DGND1

VDD33

DGND2

VIO

DGND3

VCC

AG D

BG D

InternallyTied

toSubstrate

DIX4192

SBFS031F – FEBRUARY 2006 – REVISED SEPTEMBER 2016

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9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 RESET Operation

The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the

internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset

low pulse width must be a minimum of 500 ns in length. The user must not attempt a write or read operation

using either the SPI or I2C port for at least 500 μs after the rising edge of RST. See Figure 6 for the reset timing

sequence of the DIX4192.

In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby

all registers and buffers are forced to their default settings. Refer to Control Registers for details regarding the

RESET bit function.

Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception

of the SPI or I2C host interface and the corresponding control registers. The user may then program the DIX4192

to the desired configuration, and release the desired function blocks from the power-down state using the

corresponding bits in control register 0x01.

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