LP8550TLESLASHNOPB datasheet(39/49 Pages) TI2

39 / 49 page

MCU

LP8550

VLDO

GNDs

ISET

VDDIO

PWM

SCLK

SDA

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

2.7V ± 22V

FILTER

+5V input rail

FSET

15 éH

VSYNC

COUT

CIN

10 éF

4.7 éF

CVLDO

1 éF

VDDIO reference voltage

VSYNC signal

120 k

100 nF

RISET

1 éF

FAULT

Can be left floating

if not used

39 pF

VIN

RFSET

VBATT 5.5V ± 22V

10 ± 40V, 180 ± 400 mA

10 ± 25V, 180 mA

LP8550

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SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

Figure 31. Typical Application for Low-Input Voltage

9.2.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range, VBATT

2.7 V to VOUT

5-V input rail, VLDO/VIN

4.5 V to 5.5 V, 10 mA

Brightness Control

PWM input duty cycle (default), I2C can be used as well

PWM output frequency

With RFSET resistor 85 kΩ to 100 kΩ; 9.8 kHz with PSPWM enabled

LED Current

With RISET resistor 15 kΩ; 25 mA/channel

Brightness slopes

200-ms linear slope + advanced slope

External set resistors

Enabled

Inductor

10 µH to 33 µH, with 2.5-A saturation current

Boost SW frequency

625 kHz

SW current limit

2.5 A

9.2.2.2 Detailed Design Procedure

Component selection follows Design Requirements above. VLDO capacitor voltage rating can be set based on the

5-V rail voltage specification, which must be < 5.5 V in all cases. Note that UVLO is detected from the VIN pin

voltage, not from the VBATT voltage.

9.2.2.3 Application Curves

Typical Boost and LED current behavior is seen in the Application Curves section.

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