LP8550TLXSLASHNOPB.A datasheet(34/49 Pages) TI2

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LP8550

SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014

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8.6.2.7 EEPROM Address 5

Address A5h

EEPROM ADDRESS 5 REGISTER

EN_VSYNC

DITHER[1:0]

VBOOST[4:0]

Name

Bit

Access

Description

EN_VSYNC

R/W

Enable VSYNC function

0 = VSYNC input disabled

1 = VSYNC input enabled. VSYNC signal is used by the internal PLL to generate

PWM output and boost frequency.

DITHER

6:5

R/W

Dither function controls

00 = Dither function disabled

01 = 1-bit dither used for output PWM transitions

10 = 2-bit dither used for output PWM transitions

11 = 3-bit dither used for output PWM transitions

VBOOST

4:0

R/W

Boost voltage control from 10 V to 40 V with 1-V step. If adaptive boost control is

enabled, this sets the initial start voltage for the boost converter. If adaptive mode

is disabled, the output voltage of the boost converter is directly set.

0 0000 = 10 V

0 0001 = 11 V

0 0010 = 12 V

...

1 1101 = 39 V

1 1110 = 40 V

1 1111 = 40 V

8.6.2.8 EEPROM Address 6

Address A6h

EEPROM ADDRESS 6 register

PLL[12:5]

Name

Bit

Access

Description

PLL

7:0

R/W

13-bit counter value for PLL, 8 MSB bits. PLL[12:0] bits are used when en_vsync =

1. See Table 7 for PLL value calculation.

8.6.2.9 EEPROM Address 7

Address A7h

EEPROM ADDRESS 7 REGISTER

PLL[4:0]

EN_F_RES

HYSTERESIS[1:0]

Name

Bit

Access

Description

PLL

7:3

R/W

13-bit counter value for PLL, 5 LSB bits. PLL[12:0] bits are used when en_vsync = 1. See

Table 7 for PLL value calculation.

EN_F_RES

R/W

Enable PWM output frequency set resistor

0 = Resistor is disabled and PWM output frequency is set with PWM_FREQ EEPROM

1 = PWM frequency set resistor is enabled. RFSET defines the output PWM frequency. See

PWM Frequency Setting for full description of the PWM frequencies.

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